Microprocessor-based systems and a variety of other digital circuits operate based on a clock signal. At times it is necessary to reset the clock signal generating circuit, change the frequency of the clock signal, or otherwise adjust the clock. When changing the frequency of a clock, a glitch is typically generated in the clock signal output. A glitch is a temporary malfunction in the clock; it occurs when two or more transitions (rising or falling edges) through the voltage threshold occur between sample periods. In a digitally operated circuit, a glitch will disrupt the execution of one of more machine instructions during the process of changing the clock frequency.
As an example, this phenomenon can be observed in the operation of satellite set-top boxes. In these devices, it is sometimes necessary or desirable to change the operating frequencies of the central processing unit (CPU) and double data rate (DDR) clocks. The introduction of these frequency changes would typically cause a glitch in the clock signal and may well crash the system. It is therefore necessary to interrupt operation of the set top box during frequency changes, or else reset the set-top box to overcome the disruption caused by the clock signal glitch.
Therefore, there is a general need for an improved system and method for adjusting the operation of a clock signal generating circuit used in digital systems of various types. There is also a particular need for improved clock adjustment apparatus and methods in the field of satellite set-top boxes.
The present invention will now be described with reference to the accompanying drawings. In the drawings, some like reference numbers indicate identical or functionally similar elements. Additionally, the left-most digit(s) of most reference numbers identify the drawing in which the reference numbers first appear.